Since the tunnel field-effect transistor (TFET) is a gated p-i-n transistor with a gate voltage that controls the tunneling width at the source/channel junction, carriers can be transported from the source region to the channel region by the band-to-band tunneling mechanism. The special working mechanism makes it possible for the TFET to achieve a low off-state current, a high ratio of on-state current to off-state current (, and a steep subthreshold slope (SS). Therefore, the TFET can work at the ultralow supply voltage and has become a promising device candidate to replace the metal-oxide-semiconductor field-effect transistor (MOSFET) in future low power applications.^[1–10] However, with the further dimension scaling, short channel effects (SCEs) such as drain induced barrier thinning (DIBT) will become intolerable and deteriorate the SS, ratio, and the leakage current of the TFET seriously.^[11] The multi-gate structures such as the double-gate,^[12–15] asymmetry-gate,^[16,17] and gate-all-around (GAA)^[18–23] structures have been used to suppress SCEs by improving the gate control, among which the vertical GAA-TFET has received more and more attention due to its superior electrostatic performance in low power and high speed applications and the advantages of high three-dimensional (3D) integration and compatibility with existing CMOS technology.^[21] Several studies based on the vertical GAA-TFET, e.g., hetero-junction,^[22,23] and hetero-gate-dielectric,^[24] have been made to improve the on-state current of the device. A silicide source^[21] was introduced into the process of the vertical GAA-TFET to reduce the parasitic resistances.

Inspired by the nanotube FET,^[31] we introduce a novel TFET in this work by adding a core gate to the GAA-TFET, which is called the double-gate-all-around TFET (DGAA-TFET). The performance of the novel device is studied by numerical simulation, and the obtained results show that the DGAA-TFET achieves improved , subthreshold slope, SCEs, and on-state current, as compared with the GAA-TFET.

The 3D structure and schematic cross section of the DGAA-TFET are shown in Figs. 1(a) and 1(b), respectively, and the corresponding structure and cross section of the GAA-TFET are also shown in Figs. 1(c) and 1(d) respectively for comparison. The fabrication process of the vertical DGAA-TFET, which is similar to that of the vertical GAA-TFET,^[21] is depicted in Fig. 1(e).

Fig. 1.

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	Fig. 1. (color online) (a) Schematic cross-section of the DGAA-TFET. (b) 3D structure of the DGAA-TFET. (c) Schematic cross-section of the GAA-TFET. (d) 3D structure of the GAA-TFET. (e) Fabrication process of the DGAA-TFET.

In the present study, the lengths of the drain and source regions are both fixed at 20 nm, and the channel length ranges from 10 nm to 60 nm. The doping concentrations of the drain, channel, and source regions are 1 × 10²⁰ cm⁻³, 1 × 10¹⁶ cm⁻³, and 1 × 10¹⁹ cm⁻³, respectively. The work function φ_M1 of the outer gate M1 is fixed at 4.2 eV, whereas the work function φ_M2 of the core gate M2 varies from 4.2 eV to 4.8 eV. The thickness of the gate dielectric HfO₂ is 2 nm. The body diameter of the GAA-TFET is 20 nm, which is equal to the outer diameter of the DGAA-TFET.

Simulation is conducted using Silvaco ATLAS.^[24] Since the tunneling process is nonlocal, we use a nonlocal band-to-band tunneling (BTBT) model which takes into account the spatial variation of the energy bands. The trap-assist-tunneling model (tunnel.trap) is also considered to calculate the tunneling current, and Fermi–Dirac statistics, while Shockley–Read–Hall (SRH) recombination models are included for calculating the transport characteristics. Since the drain and source regions are both highly doped, the band gap narrowing model (BGN) is included. The Lombardi mobility model (CVT) is used for the mobility effect, and the quantum confinement (QC) effect is considered, but the gate leakage is neglected in the simulation.

Figure 2 exhibits the transfer characteristics of the DGAA-TFET and GAA-TFET with the channel lengths of 10 nm and 40 nm. From Fig. 2, it is obvious that when the channel length decreases from 40 nm to 10 nm, the leakage current of the GAA-TFET at deteriorates seriously (from 10⁻¹³ A/ to 10⁻¹⁰ A/), whereas the DGAA-TFET shows less sensitivity to the channel length.

Fig. 2.

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	Fig. 2. (color online) Transfer characteristics of DGAA-TFET and GAA-TFET with channel lengths of 10 nm and 40 nm ().

Figure 3 shows the comparison between the DGAA-TFET and GAA-TFET in terms of ratio, in which the on-state current of each device is obtained under and , and the off-state current is obtained under and . It can be seen that the DGAA-TFET outperforms the GAA-TFET in terms of the ratio. When the channel length decreases to 10 nm, of the GAA-TFET is seriously deteriorated, whereas the DGAA-TFET shows less sensitivity to the channel length, which results from its thinner body^[16] and additional core gate.

Fig. 3.

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	Fig. 3. (color online) Plots of ratio versus channel length (φM2 = 4.6 eV, , 20 nm, 30 nm, 40 nm, 50 nm, 60 nm).

The plots of transconductance ( and transconductance-to-drive current ratio ( versus overdrive voltage ( for the DGAA-TFET are depicted in Fig. 4. For comparison, the corresponding characteristics of the GAA-TFET are also shown in Fig. 4. It can be found that with the increase of the gate voltage, the conductance increases. Higher of the DGAA-TFET than the GAA-TFET shows that the proposed device has stronger gate control. Additionally, the ratio is higher in the DGAA-TFET than in the GAA-TFET. The is an important device performance parameter for the analog circuit, since the transconductance represents the amplification delivered by the device, and the drain current represents the power dissipation to obtain the amplification.^[29] It is concluded that the DGAA-TFET is capable of providing a higher gain than the GAA-TFET at the same power level.

Fig. 4.

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	Fig. 4. (color online) Plots of transconductance ( and transconductance-to-drive current ratio () versus overdrive voltage of the DGAA-TFET and GAA-TFET with a channel length of 10 nm ().

Figure 5 shows a comparison of the output characteristic between the DGAA-TFET and the GAA-TFET at 10 nm channel length. Initially, the drain currents of two devices increase very rapidly with increasing drain voltage, and then the rates of increase in the drain currents decrease. Finally, the DGAA-TFET shows a good saturation of drain current at higher drain voltage. However, the GAA-TFET exhibits a different behavior at higher drain voltage, and the drain current of the GAA-TFET improves slowly with the increase of the drain voltage. To explain the phenomenon mentioned above, Figures 6(a) and 6(b) are depicted, which show the energy band diagrams for different drain voltages corresponding to of the DGAA-TFET and the GAA-TFET, respectively. For both devices, when the drain voltage is small, the band of the channel region is pinned by the drain potential. The drain voltage appears across the tunneling junction.^[30] The tunneling widths of two devices decrease with the increase of the drain voltage, and the drain currents are increased rapidly. For the DGAA-TFET, when the drain voltage is large enough, the tunneling junction is no longer affected by the increase of the drain voltage and shows a good saturation of the drain current. For the GAA-TFET, however, when the drain voltage is large enough, the change of tunneling width cannot be neglected, and the drain current is increased slightly with the increase of the drain voltage and shows a bad saturation of drain current.

Fig. 5.

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	Fig. 5. (color online) Output characteristics for three different gates. The channel length is 10 nm and .

Fig. 6.

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	Fig. 6. (color online) (a) Energy band diagrams for different values of at for the DGAA-TFET. (b) Energy band diagrams for different values of at for the GAA-TFET. , , , 0.3 V, 0.5 V, 0.7 V, 0.9 V, 1.1 V, 1.3 V, 1.5 V.

Figure 7 displays the plots of DIBT versus channel length of the DGAA-TFET and GAA-TFET, which is defined as the difference between the threshold voltages when the drain voltages are 0.1 V and 1.0 V. It can be seen when the channel length is large enough, the DIBT of the DGAA-TFET (45 mV/V) is smaller than that of the GAA-TFET (53 mV/V). We can also find that a shorter channel length will worsen DIBTs of both the DGAA-TFET and the GAA-TFET, but the DGAA-TFET shows better DIBT suppression than the GAA-TFET. In order to explain the difference, Figure 8 depicts the energy band diagrams of the GAA-TFET along the cutline and the DGAA-TFET along the cutline (2 nm away from the interface between the body and the oxide). It can be seen from Figs. 8(a) and 8(b) that when the channel length is large (40 nm), the drain voltage increases from 0.1 V to 1.0 V and the gate voltage keeps a constant (, the tunneling barrier width of the DGAA-TFET changes little, whereas the tunneling barrier width of the GAA-TFET changes obviously. The DGAA-TFET shows much less sensitivity to the drain voltage and therefore much better DIBT suppression than the GAA-TFET. When the channel length decreases from 40 nm to 10 nm, the tunneling barrier thinning of the two devices are much more obvious than that of 40 nm. However, the variation of the tunneling barrier width of the DGAA-TFET is less than that of the GAA-TFET, which means that the DGAA-TFET shows less sensitivity to the channel length than the GAA-FET. With a thinner body and a core gate, the DGAA-TFET shows stronger gate control and less sensitivity to the channel length than the GAA-TFET.

Fig. 7.

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	Fig. 7. Drain induced barrier thinning effects of the DGAA-TFET and GAA-TFET versus channel length. φM2 = 4.6 eV, LC= 10 nm, 20 nm,30 nm, 40 nm, 50 nm, 60 nm.

Fig. 8.

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	Fig. 8. (color online) (a) Energy band of GAA-TFET along . (b) Energy band of DGAA-TFET along . Both and are 2 nm away from the interface between the outside oxide and silicon.

Considering that the SS of the TFET is gate voltage dependent rather than a constant, the point subthreshold slope (SS_POINT) and average subthreshold slope (SS_AVR) are used together to depict the subthreshold characteristics. SS_POINT is defined as the minimum swing value at all points on the – curve, whereas SS_AVR is calculated between the point at which the current begins to increase with the increasing gate voltage, and the point at which the current reaches .^[27] Figure 9 compares the DGAA-TFET with GAA-TFET in terms of SS. It can be seen that the DGAA-TFET exhibits better SS than the GAA-TFET. When the channel length decreases to 10 nm, SS_AVR and SS_POINT of the GAA-TFET are seriously deteriorated, whereas the DGAA-TFET shows less sensitivity to the channel length, which results from its thinner body^[27–30] and core gate.

Fig. 9.

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	Fig. 9. (color online) Plots of subthreshold slope versus channel length. .

As shown above, the advantages of the DGAA-TFET result from its thinner body and extra core gate. To investigate the effect of the work function φ_M2, Figure 10 shows the plots of the drain current of the DGAA-TFET versus gate voltage for different values of φ_M2. From Fig. 10, it can be seen that when φ_M2 decreases from 4.8 eV to 4.2 eV, the saturation current is increased, which results from the increasing tunneling probability on the source side,^[2] caused by increasing the band overlap and reducing tunneling barrier width. However, it can also be found that when reducing φ_M2, the leakage current is deteriorated. Therefore, a trade-off should be taken into account between the on-state and off-state currents when determining the work function of the core gate.

Fig. 10.

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	Fig. 10. (color online) Transfer characteristics of DGAA-TFET with different core gate work functions. The channel length is 10 nm.

In this work, a novel double-gate-all-around tunnel field effect transistor (DGAA-TFET) is proposed. Compared with the conventional GAA-TFET, the DGAA-TFET exhibits high on-state current, good subthreshold slope, and small susceptivity to SCEs, which results from the extra core gate and thinner body. These excellent electrical characteristics make the proposed device a more attractive candidate to the further dimension scaling.